Design Verification Engineer: GLS

Semidynamics in Barcelona is seeking a Design Verification Engineer to support gate-level simulation and hardware emulation for our AI chip design teams. You will validate post-synthesis netlists, debug timing and reset issues, and enable large-scale emulation of SoC designs prior to tapeout.This hands-on role requires close collaboration with RTL design, DFT, physical design and firmware teams, plus bringing up emulation models for pre-silicon software validation and performance profiling.