Senior DFT Engineer – Avnet ASIC Israel

The company is looking for a Senior DFT Engineer to own Design-for-Test (DFT) for customer SoCs, from architecture and implementation through tape-out and production test hand-off.

Responsibilities:

• Develop and implement DFT architecture, scan insertion, and ATPG.
• Handle memory BIST, boundary scan, and at-speed testing. ● Debug DFT rule violations and improve test coverage.
• Run gate-level simulations and pattern validation.
• Perform formal equivalence checking and automate flows using scripting. ● Own the end-to-end DFT process through tape-out and production. Requirements:
• BSc in Electrical Engineering.
• Minimum 3 years of hands-on DFT experience.
• Strong knowledge of scan, ATPG, MBIST, JTAG, and fault models.
• Experience with Synopsys DFT Compiler/TestMAX or Siemens Tessent.
• Experience with gate-level simulation, formal verification, Perl/Tcl, and UNIX.
• End-to-end DFT flow ownership. Nice to have: Advanced-node experience (7nm and below), Siemens Tessent ScanPro/TestKompress/LBIST, and Python scripting.